                              ===========================                             
                              R E L E A S E    N O T E S
                              ===========================

                         QLogic 57710/1 Gigabit Ethernet Controller Bootcode

                      Copyright (c) 2015 QLogic Corporation
                                 All rights reserved.

History
=======

Version 5.2.6 (Nov 11, 2009)
============================

    Fixes:
    ------
    1.  Problem: (CQ44159) 57711E may not enumerate as such

        Cause:   Insufficient voltage margin setting for reading chip ID

        Fix:     Configure the HW differently to determine the chip ID

        Impact:  Relevant to 57711E only

Version 5.2.5 (Sep 14, 2009)
============================

    Fixes:
    ------
    1.  Problem: (CQ43416) License query on port 1 failed with INFO_NOT_READY

        Cause:   Wrong initialization of license holdoff timer for port 1

        Fix:     Correctly initialize the license holdoff timer for port 1

        Impact:  None

    2.  Problem: Possible race with pre OS driver in initialization of PHY
                 after CLP exit done command

        Cause:   Bootcode doesn't consider driver presence before calling
                 init_phy()

        Fix:     Bootcode will consider driver presence before calling
                 init_phy()

        Impact:  None

    Enhancements:
    -------------
        Request: Modify BCM8481 link led configuration in 10G

        Change:  As requested

        Impact:  None

Version 5.2.4 (Sep 3, 2009)
===========================

    Fixes:
    ------
    1.  Problem: 57711/57711E on direct boards unable to link up @ 1G using
                 auto-negotiation

        Cause:   When negotiating using CL73, 1G-KX speed wasn't advertised

        Fix:     In CL73, when 1G speed capability is enabled, advertise 1G-KX,
                 and disable 10G parallel-detect

        Impact:  None

    2.  Problem: 57711/57711E Flow control doesn't work when auto-negotiation
                 complete with CL73

        Cause:   Flow-Control wasn't advertised with CL73

        Fix:     Enable Flow-Control negotiation using CL73

        Impact:  None

Version 5.2.3 (Aug 27, 2009)
============================

    Fixes:
    ------
    1.  Problem: LLDPDU TTL value is same as LLDP transmission interval

        Cause:   LLDPDU TTL value should be (msgTxInterval * msgTxHold)

        Fix:     Set LLDPDU TTL value to (msgTxInterval * msgTxHold)

        Impact:  None

Version 5.2.2 (Aug 24, 2009)
============================

    Fixes:
    ------
    1.  Problem: (CQ43305) After upgrading to the last bootcode version, driver
                 might fail to load

        Cause:   MSIX mask bit fix is applied every MCP reset

        Fix:     Set the MSIX mask bit only after POR

        Impact:  None

Version 5.2.1 (Aug 20, 2009)
============================

    Fixes:
    ------
    1.  Problem: Version 5.2.0 cannot be loaded on 57711

        Cause:   Bad address was used in the code

        Fix:     Fixed the code to use the right offsets

        Impact:  None

Version 5.2.0 (Aug 20, 2009)
============================

    Fixes:
    ------
    1.  Problem: (CQ42528) Enabling "Prevent PCIe L1-entry" option in nvm cfg
                 caused on function to disappear

        Cause:   Wrong PCI register was changed

        Fix:     Use a different PCI register to prevent L1-entry

        Impact:  None

    2.  Problem: MSIX mask bit is cleared for all entries in MSIX table

        Cause:   Wrong reset values

        Fix:     Set the MSIX mask bit for all entries in MSIX table

        Impact:  None

    3.  Problem: Link is down with BCM8481 when connected to 1G device after
                 it was connected to 100M device

        Cause:   When link type changes from SGMII to GMII/XGMII, the SGMII
                 configuration wasn't removed

        Fix:     Remove SGMII configuration in non-SGMII link type

        Impact:  None

    4.  Problem: BCM8481 link is down after cable plug out/in

        Cause:   New BCM8481 image required new configuration of LED4 signal
                 which generate the interrupt

        Fix:     Detect link down using the LED4 signal rather than the BCM8481
                 registers

        Impact:  None

    5.  Problem: (CQ35477) Incorrect display of External Phy Firmware Version
                 for Everest XFP board

        Cause:   External Phy Firmware Version for XFP boards used to display
                 0000:0000

        Fix:     Change display in this case to "N/A"

        Impact:  None

    6.  Problem: In BCM8727, spirom was loaded first on slave port, rather than
                 on the master port. This may lead to xaui pll issue

        Cause:   Port-Swap wasn't considered when loading spirom to the BCM8727,
                 hence first the slave port was loaded with the spirom

        Fix:     First load the SPIROM to the master port

        Impact:  None

    7.  Problem: In BCM8727 base boards, link is down intermitted after loading
                 the interface

        Cause:   In BCM8727 No-OverCurrent board designs, link up registers
                 gets updated 10us after link up LASI is received

        Fix:     Add 100us delay after LASI is triggered before reading link
                 status

        Impact:  None

    Enhancements:
    -------------
    1.  Request: Add LLDP support with custom organizationally specific
                 extension

        Change:  As requested

        Impact:  None

    2.  Request: (CQ41112) PHY LED programming for BCM8481 on BlackBird
                  (BCM957711A1100G) production board

        Change:  As requested

        Impact:  None

    3.  Request: (CQ41067) Add support for CL73 to CX4 boards

        Change:  As requested

        Impact:  None

Version 5.0.11 (July 01, 2009)
==============================

    Fixes:
    ------
    1.  Problem: Link up time takes too long with BCM8727 based NICs

        Cause:   EDC mode is not set automatically

        Fix:     Set EDC mode manually according to the SFP+ module type
                 detected (Passive DAC / Active DAC / LC-LRM / LC-SR / LC-LR)

        Impact:  None

    2.  Problem: (CQ41567) In BCM8727 based NICs, when SFP+ module is not
                 plugged, there is continuous messages of Link Down

        Cause:   The EDC tries to process the Rx data/noise because its OPRXLOS
                 input signal is false (low), indicating an Rx signal is
                 present.

        Fix:     Perform Or of the Active Module Absent Level with the Active
                 Laser Loss of Light Level. This way we tell the EDC not
                 process Rx data/noise when the module is not present.

        Impact:  None

Version 5.0.10 (June 18, 2009)
==============================

    Fixes:
    ------
    1.  Problem: (CQ42071) On 57711E, MCP parity attention with old eVBD
                 versions

        Cause:   Fix from boot code 5.0.3 was broken

        Fix:     Clear spad area of 0x200 dwords (0x800 bytes) starting from
                 BC2 start address to avoid parity error if accessed by mistake
                 by driver

        Impact:  None

    Enhancements:
    -------------
    1.  Request: Disable PCI L1 entry according to nvm cfg 86

        Change:  As requested

        Impact:  None

    2.  Request: (CQ41252) Preserve the MFW data after hard reset - clear it
                 only on POR event

        Change:  As requested

        Impact:  None

Version 5.0.9 (June 08, 2009)
=============================

    Fixes:
    ------
    1.  Problem: Get licensing key works only for port zero

        Cause:   The port parameter was not taken into account in all places

        Fix:     Get the license key for the requested port

        Impact:  None

Version 5.0.8 (June 04, 2009)
=============================

    Enhancements:
    -------------
    1.  Request: Support nvram option 85 that force expansion ROM advertisement
                 even when MBA is disabled

        Change:  As requested

        Impact:  None

Version 5.0.7 (June 01, 2009)
=============================

    Fixes:
    ------
    1.  Problem: GRC timeout warning string in "mcp trace" when setting WoL

        Cause:   The correct SerDes was not selected

        Fix:     Select the correct SerDes before setting WoL

        Impact:  For 57711 and 57711E only (not 57710)

    Enhancements:
    -------------
    1.  Request: Add support for BCM8727_NOC

        Change:  As requested

        Impact:  None

    2.  Request: Support module image revision 1 without warning string

        Change:  As requested

        Impact:  Revision 0 of the module image (which was supported only by
                 bootcode version 5.0.6) is no longer supported

Version 5.0.6 (May 26, 2009)
============================

    Enhancements:
    -------------
    1.  Request: Allow enabling and disabling the fan failure mechanism for
                 different PHY types

        Change:  Determine if fan failure enforcement is required according to
                 nvram option 83 (which can indicate that the fan is related to
                 the PHY type)

        Impact:  None

    2.  Request: Add support for link using the BCM8727 PHY

        Change:  As requested

        Impact:  None

    3.  Request: Allow disabling ASPM Support according to nvm cfg option 84

        Change:  As requested

        Impact:  For 57711 and 57711E only (not 57710)

    4.  Request: Save code space by removing WoL and NCSI support from BCM8705,
                 BCM8072 and SFX7101

        Change:  As requested

        Impact:  No WoL or NCSI support on BCM8705, BCM8072 or SFX7101 PHY -
                 currently, there are no plans for production board that
                 requires those features with those PHYs

    5.  Request: Add support for DCC spec 1.6

        Change:  As requested

        Impact:  None

    6.  Request: Remove WoL and NCSI support for BCM8481

        Change:  As requested

        Impact:  No WoL nor NCSI support for BCM8481

Version 5.0.5 (May 10, 2009)
============================

    Fixes:
    ------
    1.  Problem: (CQ40370) Bootcode fail to setup 10G link

        Cause:   Incorrect writing and reading of WB registers

        Fix:     Correct the writing and reading of WB registers

        Impact:  For 57711 and 57711E only (not 57710)

    Enhancements:
    -------------
    1.  Request: Add fan failure support for BCM8727

        Change:  As requested

        Impact:  None

Version 5.0.4 (May 04, 2009)
============================

    Fixes:
    ------
    1.  Problem: Per function statistics addresses from MFW for the non PMF
                 drivers are still not initialized when the PMF driver loads

        Cause:   Only the loaded driver's per function statistics address was
                 initialized

        Fix:     Initialize all per function statistics addresses when the PMF
                 driver loads

        Impact:  None

    2.  Problem: NCSI needs to know the maximum supported functions

        Cause:   Parameter was removed from fw_info

        Fix:     Return back max_func_num to fw_info

        Impact:  None

    3.  Problem: DCC link notification packets might be send out

        Cause:   DCC link notification was partially implemented

        Fix:     Remove sending DCC link notification packets

        Impact:  None

Version 5.0.3 (Apr 27, 2009)
============================

    Fixes:
    ------
    1.  Problem: DCC is in disabled state after CLP exit done

        Cause:   DCC expects for a redundant dynamic configuration enabled bit

        Fix:     Remove the redundant bit

        Impact:  None

    2.  Problem: DCC sends link state up for unloaded driver

        Cause:   DCC didn't consider the driver state

        Fix:     Consider driver state to determine link status

        Impact:  None

    3.  Problem: DCC sends link notification up for unloaded driver

        Cause:   Link notification is sent from a static area and the link
                 status field was not updated before sending

        Fix:     Update the correct link sttaus before sending

        Impact:  None

    4.  Problem: (CQ40409, CQ40411) MCP parity attention with old eVBD versions

        Cause:   During PMF migration the driver read the port's statistics
                 from invalid address in the chip, causing HW attention

        Fix:     Clear rest of spad area of BC2 to avoid parity error if
                 accessed by mistake by driver

        Impact:  None

    Enhancements:
    -------------
    1.  Request: Clear MFW save area in shared memory after POR

        Change:  As requested

        Impact:  None

Version 5.0.2 (Apr 16, 2009)
============================

    Fixes:
    ------
    1.  Problem: Endianness issue in some u16 fields in some DCC packets

        Cause:   Bad definition of some DCC TLVs lack the 2 bytes alignment
                 required for using u16 fields

        Fix:     Swap the bytes as array of two u8 fields

        Impact:  None

    Enhancements:
    -------------
    1.  Request: Support forcing SF mode without power-cycle

        Change:  Hide the higher functions according to the nvram configuration

        Impact:  If changed from MF to SF, the higher functions will remain in
                 limbo state from the OS perceptively until reboot

Version 5.0.1 (Apr 07, 2009)
============================

    Fixes:
    ------
    1.  Problem: On 57710, Bootcode asserts if 1G SerDes link is requested
                 after driver unload

        Cause:   SerDes was set by driver to Clause45 mode

        Fix:     Re-init the SerDes to Clause22 mode

        Impact:  None

    2.  Problem: (CQ40352) Bootcode stuck after loading an old NCSI image

        Cause:   Old NCSI images are not supported

        Fix:     Check NCSI image version before loading

        Impact:  None

    3.  Problem: On 57710, Bootcode fails to setup a link when set to autoneg
                 and link-partner is set to forced speed

        Cause:   Clause73 autoneg is not working

        Fix:     Clause73 autoneg is not supported

        Impact:  None

    4.  Problem: BCM8481 is not able to link up in legacy speeds

        Cause:   Setting legacy speeds requires additional phy configuration
                 and speed analysis

        Fix:     Enable legacy speeds for this phy

        Impact:  None

    Enhancements
    ------------
    1.  Request: Eliminate possible bootcode stuck due to assert

        Change:  Convert asserts to error prints

        Impact:  None

    2.  Request: Driver can reset the NIG during unload. Restore NIG registers,
                 that were initialized by bootcode, after driver unload

        Change:  As requested

        Impact:  None

Version 5.0.0 (Apr 02, 2009)
============================

    Fixes:
    ------
    1.  Problem: On 57711/57711E, bootcode clears some latched attentions even
                 if there is a driver loaded

        Cause:   ISR didn't check if a driver is loaded

        Fix:     Clear latched attentions only if no driver is present

        Impact:  None

    2.  Problem: (CQ39172) On 57711/57711E, there might be holes in PCI INT#
                 This is not compliant with PCI specification

        Cause:   PCI INT# allocation was not correct

        Fix:     Fix PCI INT# allocation to be compliant with PCI specification

        Impact:  None

    3.  Problem: (CQ39625) On 57711/57711E, there might be signal integrity
                 issue with PCI Gen 2

        Cause:   Default PCI SerDes pre-emphasis values are not appropriate for
                 all cases

        Fix:     Config the PCI SerDes pre-emphasis according to NVRAM
                 configuration parameter

        Impact:  None

    Enhancements
    ------------
    1.  Request: Allow forcing single function mode using SGPIO4

        Change:  Enhanced option 73 in "nvm cfg" to use either fixed value or
                 SPIO4 to force single function mode. When using SPIO, high
                 means only SF, 0 is according to CLP configuration

        Impact:  None

    2.  Request: Add support for DCC

        Change:  As requested

        Impact:  None

    3.  Request: Support new NCSI image starting from version 1.0.7

        Change:  As requested

        Impact:  Old NCSI images are not supported

Version 4.8.51 (Feb 04, 2009)
=============================

    Fixes:
    ------
    1.  Problem: "ext_phy_fw version" command for BCM8706 sometimes shows
                 invalid version number

        Cause:   The version number is read during init phase. Reading the
                 BCM8706 version during init phase is done premature

        Fix:     During init phase of the BCM8706, wait until the firmware
                 is loaded completely before reading the version number

        Impact:  None

    2.  Problem: When setting pre-emphasis values for external phys, the
                 XGXS is also set

        Cause:   In external-phy boards, when pre-emphasis values were set in
                 the nvram, both the external phy and the XGXS pre-emphasis
                 values were set, while the values fit the external phy only

        Fix:     Set pre-emphasis values in XGXS only for direct type boards

        Impact:  None

    Enhancements
    ------------
    1.  Request: Improve expansion_rom_handling()

        Change:  Read from NVRAM only the requested size of dwords instead of
                 reading always the maximum (3) dwords

        Impact:  None

    2.  Request: Add ability to change BCM8726 TX PreEmphasis using nvram
                 configuration

        Change:  When nvram config "Override pre-emphasis configuration" (75)
                 is set, use Tx pre-emphasis nvram configuration (47), lane0
                 value to set the Main Tap and lane1 to enable TX-PreEmphasis
                 in BCM8726

        Impact:  None

    3.  Request: Add basic support for BCM8481

        Change:  As Requested

        Impact:  None

Version 4.8.50 (Jan 19, 2009)
=============================

    Fixes:
    ------
    1.  Problem: 1G switch configuration (using the 5th lane) doesn't work

        Cause:   Support for Serdes (5th lane) was not maintained since no
                 production design used it and when switching to CL45 it stopped
                 working

        Fix:     In order for control the Serdes over Clause45, (and not
                 Clause22), it requires first one time register setting in
                 Clause22

        Impact:  None

    Enhancements
    ------------
    1.  Request: Add support for BCM8726

        Change:  As requested

        Impact:  None

Version 4.8.0 (Oct 28, 2008)
============================

    Fixes:
    ------
    1.  Problem: Simultaneous VPD access to more than 1 function on
                 57711 caused bootcode to hang

        Cause:   The bootcode tried to determine which function tried
                 to access the VPD and failed to recognize when more
                 than one function was register for VPD access

        Fix:     The bootcode can handle all functions request

        Impact:  None

    Enhancements:
    -------------
    1.  Problem: (CQ35662) Add support for the nvm cfg options, 47, 48
                 for XGXS core

        Cause:   Current nvm values didn't actually affect the phy

        Fix:     To keep backward compatibility, only in case the
                 "Override pre-emphasis configuration" nvm option is
                 enables, it sets the the tx pre-emphasis and rx
                 equalizer values for the 4 lanes according to the "XGXS
                 backplane Tx pre-emphasis matrix coef." and "XGXS
                 backplane Rx equalizer matrix coef." respectively

        Impact:  None

Version 4.6.3 (Sep 28, 2008)
============================

    Enhancements:
    -------------
    1.   Request: Strict licensing enforcement

         Change:  As Requested.

         Impact:  Boards with older versions of the licensing scheme
                  will not support offloaded connections

    2.   Request: Support NCSI filters reconfiguration

         Change:  After the last driver is unloaded, the NCSI FW
                  receives indication so the incoming traffic filters
                  can be reconfigured

         Impact:  None

Version 4.6.2 (Sep 23, 2008)
============================

    Enhancements
    ------------
    1.  Request: Add inventory table for NCSI

        Change:  As requested

        Impact:  NCSI version 1.0.3 or later is needed. Earlier versions
                 of NCSI will not work with this bootcode

    2.  Request: (CQ36860) For 57710: use NVRAM pre-emphasis
                 configuration if this option is enabled

        Change:  In case of WoL, or NCSI the boot code will need to
                 initialize the PHY with the correct values

        Impact:  WoL and NCSI.  No impact or dependencies on device
                 drivers

Version 4.6.1 (Sep 03, 2008)
============================

    Fixes:
    ------
    1.  Problem: (CQ35240) 57711E sometimes cannot work as 57711

        Cause:   Using a configuration parameter before loading it from NVRAM

        Fix:     Load the parameter from NVRAM before using it

        Impact:  None

    2.  Problem: (CQ34605) Machine gets stuck if it gets "pause" constantly

        Cause:   Ramrods cannot pass when tx ring is full

        Fix:     Set NIG drain in case of NIG timer max event

        Impact:  None

Version 4.6.0 (Aug 24, 2008)
============================

    Enhancements
    ------------
    1.  Request: Add a mode on which SPIO4 follows PERST

        Change:  As requested (nvm cfg 78)

        Impact:  None

    2.  Request: Set PHY related G/SPIOs according to the PHY type

        Change:  As requested

        Impact:  The nvram board type entry has no effect

Version 4.5.10 (Aug 14, 2008)
=============================

    Fixes:
    ------
    1.  Problem: PCI Serial number is all zeros

        Cause:   The PCI serial number was not initialized from the
                 NVRAM

        Fix:     Initialize the PCI serial number

        Impact:  None

Version 4.5.9 (Aug 14, 2008)
============================

    Fixes:
    ------
    1.  Problem: WoL after POR sometimes fails

        Cause:   The 8073 SPI-ROM loading fails

        Fix:     Retry the SPI-ROM loading

        Impact:  None

Version 4.5.8 (Aug 12, 2008)
============================

    Fixes:
    ------
    1.  Problem: XAUI link on port0 goes down and then up, when the link
                 on port1 is changed

        Cause:   When master port (port1) is down, it will also cause
                 the blade side down. In turn, PLL will change speed
                 from 10G to 1G. It will cause XAUI clock to both ports
                 down and then up again

        Fix:     Set bit in the BCM8073 that enables the fix

        Impact:  None

Version 4.5.7 (Aug 10, 2008)
============================

    Fixes:
    ------
    1.  Problem: (CQ36772) KR with 8073 PHY sometimes does not establish
                 link

        Cause:   A missing delay between initializing the PHY SPI ROM
                 and inserting the PHY back to low power mode

        Fix:     Add 15ms delay after loading the SPI PHY ROM which is
                 before entering low power mode

        Impact:  None

    2.  Problem: (CQ36773, CQ36777, CQ36778) WoL with 8073 PHY sometimes
                 establish link with the switch but there is no link
                 between the 5771x and the 8073 PHY

        Cause:   The port initializing started before the SPI-ROM ended

        Fix:     Do not start port initialization before SPI-ROM
                 download to the PHY ended

        Impact:  None

Version 4.5.6 (Aug 08, 2008)
============================

    Fixes:
    ------
    1.  Problem: When upgrading 8073 SPI ROM PHY to version 0103 the
                 link will not come up

        Cause:   Register 0x8370 is no longer required in the new
                 version and writting to it cause the link not to come
                 up

        Fix:     Remove the wirte to address 0x8370

        Impact:  None

Version 4.5.5 (Aug 07, 2008)
============================

    Fixes:
    ------
    1.  Problem: On some KR boards when loading driver on port0, and
                 port1 is not loaded, sometimes the XAUI link is not
                 coming up and sometimes when unloading driver on port1
                 port 0 might loose link

        Cause:   The 8073 PHY has two ports that share a single clock.
                 This clock is routed to a port deemed to be the master
                 (port 1), and then a PLL at the master sets the clock
                 frequency and routes the buffered clock to both the
                 master XAUI interface as well as the slave (port 0)
                 XAUI interface. If port 0 is loaded while the 8073 PHY
                 SPI ROM is not loaded, the PLL for port 0 is not
                 guaranteed to lock. If port 1 is unloaded while port 0
                 is in use, the port 0 PLL might loose lock

        Fix:     First driver to be loaded reset and download SPI ROM on
                 both ports of the 8073 PHY during one-time
                 initialization and no driver will reset the 8073 PHY.
                 The bootcode is resetting the PHY when the last driver
                 is unloaded and then set the link for both ports for
                 WoL according to driver and nvram configuration

        Impact:  The 8073 PHY is only reset when both ports are brought
                 down

Version 4.5.4 (July 28, 2008)
=============================

    Fixes:
    ------
    1.  Problem: (CQ36510) Link LED does not turn off when 1G link is
                 lost when external PHY is present

        Cause:   The current code manually turned off the 10G LED but
                 did not handled other speeds which are controlled by HW.
                 Since the HW detect link with the external PHY, the
                 link LED stayed on

        Fix:     Turn off the LED for all speeds manually when link goes
                 down

        Impact:  None

Version 4.5.3 (July 17, 2008)
=============================

    Fixes:
    ------
    1.  Problem: MFW fails to check if driver is present or not

        Cause:   The function that validates the driver state should
                 set the heap pointer and it should be set back on exit

        Change:  Change the heap pointer when calling the function

        Impact:  The MFW should set the heap pointer back after calling
                 this function

    2.  Problem: The 8073 was put into high power mode even if not used

        Cause:   The 8073 was set to high power mode after every reset

        Change:  The 8073 will be set to high power mode only if needed

        Impact:  Any component that uses the 8073 will need to set it
                 to high power mode before using it

    3.  Problem: Port Swap is not working on 57711

        Cause:   In the 57711 the GPIOs are also swapped by default when
                 port swap is used

        Change:  Revert the GPIO swapping by bootcode after reset to
                 maintain the same flow in the drivers for 57710 and
                 57711

        Impact:  The GPIO are not swapped on the 57711 when swapping is
                 enabled

    4.  Problem: Tx Pause were not send on 1G link

        Cause:   Missing initialization to the EMAC TX_MODE

        Change:  Set FLOW_EN bit in the TX_MODE in addition to the
                 EXT_PAUSE_EN

        Impact:  None

    5.  Problem: (CQ36361) Changing speed to 1G on KR switch side
                 results in no link in OS

        Cause:   When Serdes is configured to 1G, it should remove
                 setting MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL bit in
                 MDIO_REG_BANK_SERDES_DIGITAL

        Change:  Unset MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL bit for
                 every link change

        Impact:  None

    Enhancements
    ------------
    1.  Request: Optimize link setup and support 2.5G

        Change:  Link will be configured on the external PHY before
                 setting up the internal PHY. When needed, only the
                 external PHY will be configured to autoneg. The
                 internal PHY will be set to the obtained speed

        Impact:  None

    2.  Request: BC2 on 57710 does not support loading old MFW
                 (i.e. IPMI or UMP)

        Change:  As requested

        Impact:  None

Version 4.5.2 (July 07, 2008)
=============================

    Fixes:
    ------
    1.  Problem: (CQ36180) VBD upgrade/downgrade on 57711 might result
                 in BSOD

        Cause:   The driver mailbox was cleared as if power transition
                 occurred

        Change:  Check the condition to clear the mailbox only after
                 power transition

        Impact:  None

    2.  Problem: Possible GPIO change for second port

        Cause:   Version 4.5.1 changed the GPIO register without HW lock
                 and thus created a rare race with the driver of the
                 other port

        Change:  Acquire HW lock when the other driver might be up when
                 changing GPIO status

        Impact:  None

    Enhancements
    ------------
    1.  Request: Support 57710 on the T4.5 branch

        Change:  As requested - a separate image is created for 57711
                 and for 57710

        Impact:  None

Version 4.5.1 (July 04, 2008)
=============================

    Fixes:
    ------
    1.  Problem: (CQ35420) System hang during driver load/unload stress
                 testing

        Cause:   Earlier generations of chipset do have problems when
                 the PCI-E link is driven "aggressively" into L1, while
                 in D3H. In case the downstream LOM/NIC decided to
                 re-enter L1 (while in D3H) and the upstream PCI-E link
                 partner (chipset) is waiting for an outstanding split
                 response (from the downstream LOM/NIC) it is possible
                 for certain chipsets to not enter L1.  This in return
                 will cause a DEADLOCK of the PCI-E link what ultimately
                 will lead to a system error (e.g. system reboot, or
                 hang)

        Change:  In order to not expose this chipset anomaly, we  will
                 now prevent the PCI-E link from re-entering L1 while in
                 D3H. This may not be a 100% fix for all chipsets, but
                 will significantly reduce the exposure to this
                 interoperability issue.

        Impact:  no functional system impact, though the power
                 consumption is minimal higher while in D3H.

    2.  Problem: Failed to WoL according to driver's request when nvram
                 was not configured for OOB WoL

        Cause:   The EMAC block was reset after each link changed and so
                 driver's settings were lost

        Change:  The emac is reset only when setting up the link

        Impact:  None

    3.  Problem: Driver's MAC address was not used in WoL

        Cause:   The EMAC block was reset after each link changed and so
                 driver's settings were lost

        Change:  The emac is reset only when setting up the link. The
                 driver's MAC address needs to be saved by the bootcode
                 and reprogrammed to the EMAC

        Impact:  None

    4.  Problem: WoL did not work if magic packet was received before
                 the device entered D3

        Cause:   The WoL was triggered due to the first magic packet and
                 so a new magic packet (the first in D3) did not make
                 any effect

        Change:  The magic packet indication is cleared whenever power
                 goes down and the emac is enabled

        Impact:  None

    5.  Problem: (CQ35786) S5 WoL did not work after Windows shutdown

        Cause:   The bootcode reset the MAC twice - the second time
                 erased the MAC address

        Change:  The bootcode finish initializing the link before
                 acknowledging the driver request

        Impact:  In case a link is needed (like in the WoL case) driver
                 unload will take longer due to waiting for the MCP to
                 initialize the link (but not waiting for link to come
                 up)

    6.  Problem: (CQ35846) S5 WoL did not work on second port after OS
                 shutdown

        Cause:   The second port PHY was not set to high power mode

        Change:  Set the second port to high power mode when needed

        Impact:  None

    7.  Problem: (CQ36047, CQ36057) Windows driver fails to re-load when
                 WoL enabled in NVRAM (will fail in many configuration
                 changes that involves driver unload behind the scenes
                 like MTU change and diagnostic tests)

        Cause:   The bootcode returned unload response twice - first
                 time to allow the driver to finish unloading without
                 waiting for the bootcode to set the PHY and the second
                 time after the PHY initialization was done. The second
                 response was received after the driver reloaded and
                 caused the failure

        Change:  Hold the driver unload response until the link is
                 initialized

        Impact:  In case a link is needed (like in the WoL case) driver
                 unload will take longer due to waiting for the MCP to
                 initialize the link (but not waiting for link to come
                 up)

Version 4.5.0 (May 26, 2008)
============================

    Fixes:
    ------
    1.  Problem: Potential OS freeze when disabling or uninstalling
                 drivers

        Cause:   Per PCI specification, when the LOM is put into D3-Hot
                 (D3H), it will initiate the PCI-E link to transition
                 from L0 to L1. It is still possible for the system to
                 'talk' to the LOM while in D3H, using configuration
                 read and write cycles. So when the upstream chipset is
                 sending those commands, the link temporarily returns to
                 L0 before the downstream LOM initiates the link to
                 return back into L1. The time prior to driving the
                 PCI-E link back into L1 while in D3H is 8 usec (HW
                 default). We have observed that this time is rather
                 aggressive and may cause certain chipsets to lock up
                 during the L0->L1 transition what may freeze the
                 system, or can even cause a BSOD, depending on the
                 chipset configuration.

        Change:  Extend the L1 re-entry delay from 8 usec to 16 usec.

        Impact:  None

    Enhancements
    ------------
    1.  Request: Support 8073 external PHY for 57711E

        Change:  As requested

        Impact:  None

    2.  Request: Support WoL for 57711E

        Change:  As requested

        Impact:  None

    3.  Request: Retry to set the link after POR every ~15 seconds

        Change:  As requested

        Impact:  None

Version 4.4.6 (May 07, 2008)
============================

    Fixes:
    ------
    1.  Problem: (CQ34943, CQ34968, CQ35003) Bootcode asserts after
                 driver unload when WoL is enabled

        Cause:   The driver changed the NIG to CL45 and the bootcode is
                 using CL22

        Change:  Change the NIG to CL22 before initializing the link

        Impact:  None

    2.  Problem: On some boards (T1000, A1020G and T1015G) the link
                 was establish after reset

        Cause:   The bootcode took the external PHY out of reset

        Change:  The bootcode does not touch the external PHY

        Impact:  Older drivers that counted on the bootcode to take the
                 PHY out of reset will not work with the new bootcode

Version 4.4.5 (April 28, 2008)
==============================

    Fixes:
    ------
    1.  Problem: Eliminate possible time out on host access to the NVRAM
                 at the same time when the boot code is loading
                 management firmware

        Cause:   The MCP checked the lock register constantly and
                 blocked the driver access to it

        Change:  Added delay between NVRAM polling

        Impact:  None

    Enhancements
    ------------
    1.  Request: Enhance VMAC support to persist until cold boot

        Change:  Reserve area at start of MCP scratch pad to store the
                 virtual MAC addresses

        Impact:  BC1 and MFW moved to start at address 0x08000020


Version 4.4.4 (April 1, 2008)
=============================

    Fixes:
    ------
    1.  Problem: 57711 MSI configuration is broken

        Cause:   More than one function can ask for MSI configuration
                 at a given time

        Change:  Work on all functions that request MSI configuration

        Impact:  None

    2.  Problem: 57711 driver cannot unload after missing a periodic
                 heartbeat

        Cause:   The driver port was not extracted correctly

        Change:  Fixed the code to extract the driver port

        Impact:  None


Version 4.4.3 (April 1, 2008)
=============================

    Enhancements
    ------------
    1.  Request: Changing the default interrupts for 57711 to use INT-C
                 and INT-D as well

        Change:  As requested

        Impact:  None

    2.  Request: Add attentions (debug) for reserved GRC access

        Change:  As requested

        Impact:  None

    3.  Request: Enable interrupts for 57711

        Change:  As requested

        Impact:  None

    4.  Request: Clear all 57710 A0 support

        Change:  Removed PERST detection and core clock changes

        Impact:  None

    5.  Request: Always reload PCI configuration on 57711

        Change:  As requested

        Impact:  None

    6.  Request: Allow the driver to resume after not responding in
                 57711

        Change:  As requested

        Impact:  None


Version 4.4.2 (March 20, 2008)
==============================

    Fixes:
    ------
    1.  Problem: Wrong link indication after driver unload on 57711

        Cause:   Link indication was cleared on every driver unload

        Change:  Clearing the link indication only when needed

        Impact:  None

    Enhancements
    ------------
    1.  Request: Enumerate 8 functions on PCI only if 57712 chip or
                 FPGA/Emulation

        Change:  As requested

        Impact:  None


Version 4.4.1 (March 11, 2008)
==============================

    Fixes:
    ------
    1.  Problem: Functions were not accessible when some functions
                 were disabled

        Cause:   There is a different MEMORY_SPACE control register for
                 each function

        Change:  Fix to access with the correct function

        Impact:  None

    Enhancements
    ------------
    1.  Request: Set defaults to all CLP fields

        Change:  As requested

        Impact:  None

    2.  Request: Update the statistics structure

        Change:  As requested

        Impact:  None


Version 4.4.0 (March 03, 2008)
==============================

    Enhancements
    ------------
    1.  Request: (CQ32483) Add VMAC support

        Change:  As requested

        Impact:  None

    2.  Request: Add TOE Handshake support

        Change:  As requested

        Impact:  None

    3.  Request: Remove 57710-A0 Support

        Change:  As requested

        Impact:  A0 chips will not work with this bootcode

    4.  Request: Add 57711 Support in a different binary

        Change:  As requested

        Impact:  There are two binaries for each release starting with
                 this one


Version 4.2.0 (February 03, 2008)
=================================
*** This version requires  driver 4.2.x (0.42.x) or above! ***

    Enhancements
    ------------
    1.  Request: (CQ33571) new 'shared memory' layout for T4.0E/T4.2 that will
                 be compatible with T4.4 new features

        Change:  As requested

        Impact:  All drivers (including pre-boot) must be 4.2.x or above


Version 4.0.14 (January 27, 2008)
=================================

    Enhancements:
    -------------

    1.  Request: Set SPIO 4 to high output after reset on the A1021G and A1022G

        Change:  As requested

        Impact:  None

    2.  Request: Include the chip ID in the combined bootcode image

        Change:  As requested

        Impact:  None

Version 4.0.13 (January 16, 2008)
=================================

    Fixes:
    ------
    1.  Problem: No traffic LED blink on Rx traffic in less then 10G link speed

        Cause:   For link speeds below 10G, the LED blink is controlled by the
                 bootcode. The bootcode checked only the Tx statistics when it
                 should check the Rx statistics as well

        Change:  Check both Rx and Tx statistics

        Impact:  None

    2.  Problem: (CQ #33400) Remove the 'D' (for debug) and the image type from
                 the version string

        Cause:   The redundant information was part of the string

        Change:  Removed the 'D' and the version string

        Impact:  None

    Enhancements:
    -------------

    1.  Request: Supporting the GPIO and SPIO setting for A1021G

        Change:  As requested

        Impact:  None

Version 4.0.12 (January 01, 2008)
=================================

    Enhancements:
    -------------

    1.  Request: Use hard reset and not iPOR in case of unprepared core reset

        Change:  As requested

        Impact:  None

    2.  Request: Add fan failure detection and PHY power down for the A1022G

        Change:  In case of continues 10 seconds fan failure (indicated by
                 SPIO5) on the A1022G, the MCP will shutdown the PHY. (reset
                 and low power mode, using GPIO1+2)

        Impact:  None

    3.  Request: Increasing the FW reserved space in the shared memory for
                 NC-SI support

        Change:  The FW space was increased to 440 bytes instead of 320

        Impact:  None

    4.  Request: Change the PCI device acceptable LOS and L1 latency
                 capabilities

        Change:  After POR and hard reset, the PCI device acceptable LOS and L1
                 latency capabilities were updated

        Impact:  None

    5.  Request: (CQ 32505) Report the type of the active MFW

        Change:  The validity map now includes 3 bits to indicate which MFW is
                 active

        Impact:  None

    6.  Request: Clear the iscsi boot signature and offset after every reset

        Change:  As requested

        Impact:  None

Version 4.0.11 (December 14, 2007)
===================================

    Fixes:
    ------
    1.  Problem: Unprepared reset without PERST did not cause hard reset

        Cause:   The unprepared recovery scheme assumed that every reset will
                 be accompanied by PERST and in some cases this is not true

        Change:  After core reset, if the unprepared bit is set, the MCP will
                 force hard reset

        Impact:  The MCP should not be reset while the driver is loaded or else
                 the MCP will cause hard reset

    2.  Problem: The PCI common clock bit is set

        Cause:   The common clock was set as a partial workaround for an issue
                 in A0 silicon

        Change:  The setting was removed (even in A0 since it did not make much
                 different)

        Impact:  A0 might have more stability issues but the statistics is not
                 proven

    3.  Problem: The device was not accessible if BAR1 was set to 0 in the nvram

        Cause:   The bootcode programmed BAR1 to 0, and therefore the driver
                 could not access the device any more

        Change:  Avoid programming a value of zero to BAR1

        Impact:  This is a silence discard of a wrong nvram configuration,
                 other values in the nvram can still cause damage

    4.  Problem: The device was lost if the PCI ID was set to something
                 different then BRCM 5710

        Cause:   The ediag only recognize the BRCM 5710 chip

        Change:  Avoid programming a value different then 0x14e4164e

        Impact:  This is a silence discard of a wrong nvram configuration,
                 other values in the nvram can still cause damage

    Enhancements:
    -------------

    1.  Request: Supporting the GPIO setting for A1022G

        Change:  As requested

        Impact:  None

    2.  Request: Setting the output GPIO's to a definite value

        Change:  Whenever a GPIO is "set" validate that it is not "clear" and
                 vice versa

        Impact:  None

Version 4.0.10 (November 15, 2007)
===================================

    Fixes:
    ------
    1.  Problem: MCP Fatal error when working with invalid SerDes/XGXS

        Cause:   The MCP attempted to access the SerDes/XGXS even when
                 it was not connected

        Change:  Check the nvram configuration to validate that the SerDes
                 or XGXS is connected

        Impact: None

    2.  Problem: (CQ #32064) System hangs at POST after enabling MBA on A1

        Change:  The chip revision and metal version were read in reverse order
                 so A1 seems like B0 and therefore skipped the expansion ROM
                 ECO and thus the MCP kept serving the same interrupt

        Fix:     Reversing the metal and revision order in the bootcode

        Impact:  None

    3.  Problem: Licensing information was not decoded properly

        Change:  Port 1 licensing information was read into port 0 area
                 and thus killed both ports licensing information

        Fix:     Port 1 is now read into the right location

        Impact:  None

    4.  Problem: (CQ #31120) The traffic LED was not active for lower
                 speeds

        Cause:   A workaround in the main loop is required to set the traffic
                 LED when the speed is less then 10G (using the emac and not
                 the bmac)

        Change:  The set LED routine was updated and a new function which is
                 called at least once every 5ms was added

        Impact:  None

    Enhancements:
    -------------

    1.  Request: Read the MAC address from the NVRAM rather than from the
                 shared memory to overcome a licensing failure when VMAC is
                 applied on NIC

        Change:  As requested

        Impact:  None

    2.  Request: Support dynamic (via SPIO) port swap in A1 or later

        Change:  Reading the SPIO on top of the nvram setting (xoring the
                 two)

        Impact:  None

    3.  Request: Clearing the MCP scratchpad parity error after every reset
                 and not just after POR

        Change:  As requested

        Impact:  None

    4.  Request: Support the same licensing structure is Xinan

        Change:  Changed the licensing structure to the Xinan structure

        Impact:  The shared memory mapping was shifted due to this change and
                 the STORM FW need to use a new location as well.
                 Another limitation is that the BCM57710 will only support 64K
                 licensed connections
                 The MFW (UMP and IPMI) must be of version 4.0.10 or later as
                 well

Version 4.0.9 (October 08, 2007)
===================================

    Fixes:
    ------
    1.  Problem: A0 Workarounds are applied on A1 chip

        Cause:   The A0 value cleared any Ax version

        Fix:     Check the chip metal revision as well as the chip
                 revision.


    2.  Problem: IPMI problems while Linux driver is loaded

        Cause:   The UMP pointer was translated to host point of view
                 which caused NULL pointer to be translated into GRC
                 address 0xA0000 (the location of the IPMI FW on the
                 MCP scratchpad). Only the Linux driver supported the
                 UMP statistics until this bootcode version, and so,
                 when IPMI was enabled and Linux driver was loaded,
                 the IPMI behavior is unexpected

        Fix:     When UMP FW is not present, the UMP statistics pointer
                 will appear as NULL pointer from the driver perspective
                 as well and the driver will not update them.


    Enhancements:
    -------------

    1.  Removing the debug PCI counters from version 4.0.7
    2.  Changing the licensing scheme to STORM polling
    3.  Supporting nvram function hide configuration
    4.  Supporting NC-SI image load
    5.  Not masking the NIG interrupts even if the NIG attention is not
        desired to support driver timeout due to debug break-point.
    6.  Making sure that the driver is marked as present whenever it sends
        a driver pulse (allows partial recovery from missing a pulse)


Version 4.0.8 (September 24, 2007)
===================================

    Fixes:
    ------
    1.  Problem: GRC Timeout when working in 10Mbit

        Cause:   The GRC timeout period was too short for the emac when
                 the clock was 10MHz

        Fix:     Enhanced the GRC timeout value.

    Enhancements:
    -------------

    1.  Releasing the GRC timeout attention only if there is no driver
        present.
    2.  Adding support for the T1003G


Version 4.0.7 (August 30, 2007)
===================================

    Enhancements:
    -------------

    1.  Adding a procedure to save PCI counters for the FF bug investigation


Version 4.0.6 (August 27, 2007)
===================================

    Fixes:
    ------

    1.  Problem: No MBA after warm-boot

        Cause:   The PCI parameters were set only if the PCI link training
                 hold-off succeeded.

        Fix:     Setting the PCI parameters regardless of the link hold-off
                 State.

    2.  Problem: No PCI link in case MFW is enabled and not present

        Cause:   Fatal error in case the MFW load failed

        Fix:     Replacing the fatal error with a debug print

    3.  Problem: Setting the MDIO voltage nvram configuration to 1.2V required
                 full power cycle.

        Cause:   The MDIO voltage controller was only set according to the nvram
                 configuration and not cleared.

        Fix:     Clearing the MDIO voltage bit when set to 1.2V

    Enhancements:
    -------------

    1.  Setting the Beacon according to NVRAM configuration
    2.  Improving the 10G link support (which is not part of the release)

Version 4.0.5 (August 13, 2007)
===================================

    Enhancements:
    -------------
    1.  Setting to PCI common clock (Adding partial workaround
        for the core reset bug/the FF bug)


Version 4.0.4 (August 09, 2007)
===================================

    Enhancements:
    -------------
    1.  Disabling licensing functionality
    2.  Clearing the GRC timeout attention only if driver is not present


Version 4.0.3 (August 09, 2007)
===================================

    Fixes:
    ------
    1.  Problem: Driver was assumed to be not responding

        Cause:   Cyclic calculation error on the driver pulse timeout

        Fix:     Fixed the driver pulse time stamp check

    2.  Problem: Single port device will not function after clearing
                 the nvram configuration and setting it from scratch

        Cause:   The PCI vendor ID was checked on the disabled function
                 as well and an ASSERT condition was activated if it was
                 invalid.

        Fix:     Remove the assert due to invalid PCI vendor ID

    Enhancements:
    -------------

    1.  Change the VAUX enable/disable default value in A0
    2.  Enable MSI-X on main power on event
    3.  Adding automation to the image new naming format
        (<XX>710v<Major><Minor>.<Build>)
    4.  Enabling the licensing code (changing the boundaries of BC2
        and UMP/IPMI to support it).
    5.  Loading the L2B FW in phases to allow MFW to run between the
        load time of each STORM
    6.  Adding Busy indication while loading the L2B FW
    7.  Integrating bug fixes to the link code from Windows/Linux drivers
    8.  Removing the GRC time-out assert (only debug print report)
    9.  UMP - reducing the size of some debug print to reduce code size
    10. UMP - using the emac auto clear statistics registers


Version 4.0.2 (July 10, 2007)
===================================

    Fixes:
    ------
    1.  Problem: Traffic blink rate was not working properly

        Cause:   The values of the link rate were wrong

        Fix:     Use new set of blink rate values

    Enhancements:
    -------------
    1.  Added support for T1015G (NOAC)


Version 4.0.1 (June 14, 2007)
===================================

    Enhancements:
    -------------

    1.  Switched to new compiler gcc-3.4.6
    2.  IPMI - Fix to handle Directed SMBus ARP commands (ResetDevice
        and GetUDID) after AssignAddress command
    3.  UMP - Workaround for CQ28981 - BCM57710: UMP: INGRESSBURST_DONE
        event is not issued for more than 10 sec - reset the UMP ingress
        (MAC and FIO interface) side after time out
    4.  UMP - Workaround for CQ29602 - BCM57710: UMP: Egress FIFO indicates
        incorrect byte count if LAN cable is disconnected while egress
        traffic is running - flush egress packets if NIG is still busy after
        time out in order to prevent running into egress FIFO full

